AZP94 ecl/pecl 1, 2 clock generation ch ip with tristate compatible outputs 1630 s. stapley dr., suite 127 ? mesa, arizona 85204 ? usa ? (480) 962-5881 ? fax (480) 890-2541 www.azmicrotek.com arizona microtek, inc. features ? green and rohs compliant / lead (pb) free package available ? 3.0v to 5.5v operation ? selectable divide ratio ? selectable enable polarity and threshold (cmos/ttl or pecl) ? tristate compatible outputs ? input buffer powers down when disabled ? selectable input biasing ? high bandwidth for 1ghz ? available in a mlp 8 (2x2) package ? ibis model file available on arizona microtek website description the AZP94 is a specialized 1 or 2 clock generation part including an enable/reset function. the divide ratio is selected with the div-sel pin/pad. wh en div-sel is open (nc), the AZP94 f unctions as a standard receiver. if div-sel is connected to v ee , it functions as a 2 divider. enable (en) functionality is selected with the en-s el pin/pad which has three valid states: open (nc), v ee , or connected to v ee via a 20k 20% resistor. leaving en-sel open or connecting it to v ee allows the en pin/pad to function as an active high cmos/ttl enable. when en-sel is open, an internal 75k pull-up resistor is selected which enables the outputs whenever en is left open. when en-sel is connected to v ee , an internal 75k pull- down resistor is selected which disables the outputs whenever en is left open. connecting the en-sel to v ee with a 20k resistor will allow the en pin/pad to function as an active low pecl/ecl enable with an internal 75k pull-down resistor. in this mode, outputs are enabled when en is left open (nc). the default logic condition can be overridden by connecting the en to v cc with an external resistor of 20k . if the enable signal is cmos (rail-to-rail) and the logic sense is active low (en-sel connected to v ee with a 20k resistor), the en pin/pad voltage swing must be reduced using two external resistors. contact the factory for details. when the AZP94 is disabled, the q and q outputs are forced low and the input buffer is powered down to minimize feed through. this feature a llows tristate compatible parallel output connections. multiple AZP94 chip outputs can be wired together. since both outputs are forced low in the disable mode, an enabled AZP94 can drive the output lines without interference from the unselected units. in addition, the AZP94 can be used in parallel connection with pecl/ecl parts whose outputs are high impedance when disabled. the en pin/pad also functions as a reset when the 2 mode is selected. in the 2 m ode, the counter resets when the outputs are disabled. package availability package part no. marking notes mlp 8 (2x2) green / rohs compliant / lead (pb) free AZP94nag j4g 1,2 die AZP94xp n/a 3,4 1 add r1 at end of part number for 7 inch (1k parts), r2 for 13 inch (2.5k parts) tape & reel. 2 date code format: ?y? for year followed by ?ww? for week. 3 waffle pack, die thickness 180. 4 contact factory for availability.
AZP94 april 2007 rev 1 www.azmicrotek.com 2 mlp 8, 2x2 mm package (AZP94na) the AZP94na provides a v bb with an 1880 internal bias resistor from d to v bb . this feature allows ac coupling with minimal external components. the v bb pin supports 1.5ma sink/source current and should be bypassed to ground or v cc with a 0.01 f capacitor. die (AZP94x) the AZP94x provides a v bb and a bias pad with 940 internal resistors from d to bias and d to bias. connecting the bias pad to v bb allows d and d to be ac coupled with minima l external components. for single ended applications, d or d may be connected directly to v bb to form a single 1880 bias resistor. the v bb pin supports 1.5ma sink/source curr ent. whenever used, the v bb should be bypassed to ground or v cc with a 0.01 f capacitor. typical tristate compatible operation tristate compatible operation the outputs of the AZP94 are emitter followers as shown in the left side of the drawing. when a part is disabled, both outputs are set in the low state. this allows a high output from an enabled part to override a disabled output and pull the combined line high as seen in the right hand side of the drawing. when the enabled part output is low, the combined line remains low. if all connected AZP94 parts are disabled, both output lines will be in the low state. note: the specifications in the ecl/pecl tables are va lid when thermal equilibrium has been established.
AZP94 april 2007 rev 1 www.azmicrotek.com 3 timing diagram signal description pin/pad function d/d data inputs q/q data outputs v bb reference voltage output bias input bias return en enable/reset input en-sel enable logic select div-sel divide ratio select v ee negative supply v cc positive supply enable truth table en-sel en q q nc nc cmos low or v ee 1 cmos high, v cc or nc low data low data v ee v ee cmos low, v ee or nc 1 cmos high or v cc low data low data 20k to v ee 20k to v ee pecl low, v ee or nc 1 pecl high or v cc data low data low 1 counter reset for 2 ratio divide truth table div-sel divide ratio nc 1 v ee 1 2 1 div-sel connection must b e
AZP94 april 2007 rev 1 www.azmicrotek.com 4 die pad coordinates name signal x (microns) y (microns) a d -342.5 312.5 b d -342.5 144.5 c bias -342.5 -87.0 d v bb -342.5 -255.0 e en -33.5 -312.5 f v ee 126.5 -312.5 g div-sel 312.5 -248.5 h q 312.5 -98.5 i q 312.5 51.5 j nc 312.5 201.5 k v cc 302.5 342.5 l v cc 142.5 342.5 m en-sel -140.5 342.5 note: 1. the die backside may be left open or connected to v ee . AZP94na mlp 8, 2x2 mm top view a m lk j i h g f e d c b die size: 950 x 940 bond pad: 85 x 85 die thickness: 180 AZP94
AZP94 april 2007 rev 1 www.azmicrotek.com 5 absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v cc pecl power supply (v ee = 0v) 0 to +6.0 vdc v i pecl input voltage (v ee = 0v) 0 to +6.0 vdc v ee ecl power supply (v cc = 0v) -6.0 to 0 vdc v i ecl input voltage (v cc = 0v) -6.0 to 0 vdc i hgout output current ? continuous ? surge 50 100 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c 100k ecl dc characteristics (v ee = -3.0v to -5.5v, v cc = gnd) -40 c 0 c 25 c 85 c symbol characteristic min max min max min max min max unit v oh output high voltage 1 -1085 -880 -1025 -880 -1025 -880 -1025 -880 mv v ol output low voltage 1 -1900 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mv v ih input high voltage d/d , en (ecl) 2 en (cmos) 3 -1165 v ee +2000 -740 v cc -1165 v ee +2000 -740 v cc -1165 v ee +2000 -740 v cc -1165 v ee +2000 -740 v cc mv v il input low voltage d/d , en (ecl) 2 en (cmos) 3 -1900 v ee -1475 v ee + 800 -1900 v ee -1475 v ee + 800 -1900 v ee -1475 v ee + 800 -1900 v ee -1475 v ee + 800 mv v bb reference voltage -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 mv i ih input high current en 150 150 150 150 a i il input low current en (ecl) 2 en (cmos) 3 0.5 -150 0.5 -150 0.5 -150 0.5 -150 a i ee power supply current 1 34 34 34 37 ma 1. specified with outputs terminated through 50 resistors to v cc - 2v. 2. en-sel connected to v ee through a 20k resistor 3. en-sel connected v ee or left open (nc) 100k lvpecl dc characteristics (v ee = gnd, v cc = +3.3v) -40 c 0 c 25 c 85 c symbol characteristic min max min max min max min max unit v oh output high voltage 1,2 2215 2420 2275 2420 2275 2420 2275 2420 mv v ol output low voltage 1,2 1400 1745 1400 1680 1400 1680 1400 1680 mv v ih input high voltage 1 d/d , en (pecl) 3 en (cmos) 4 2135 2000 2560 v cc 2135 2000 2560 v cc 2135 2000 2560 v cc 2135 2000 2560 v cc mv v il input low voltage 1 d/d , en (pecl) 3 en (cmos) 4 1400 gnd 1825 800 1400 gnd 1825 800 1400 gnd 1825 800 1400 gnd 1825 800 mv v bb reference voltage 1 1910 2050 1910 2050 1910 2050 1910 2050 mv i ih input high current en 150 150 150 150 a i il input low current en (pecl) 3 en (cmos) 4 0.5 -150 0.5 -150 0.5 -150 0.5 -150 a i ee power supply current 2 34 34 34 37 ma 1. for supply voltages other that 3.3v, use the ec l table values and add supply voltage value. 2. specified with outputs terminated through 50 resistors to v cc - 2v. 3. en-sel connected to v ee through a 20k resistor 4. en-sel connected v ee or left open (nc)
AZP94 april 2007 rev 1 www.azmicrotek.com 6 100k pecl dc characteristics (v ee = gnd, v cc = +5.0v) -40 c 0 c 25 c 85 c symbol characteristic min max min max min max min max unit v oh output high voltage 1,2 3915 4120 3975 4120 3975 4120 3975 4120 mv v ol output low voltage 1,2 3100 3445 3100 3380 3100 3380 3100 3380 mv v ih input high voltage 1 d/d , en (pecl) 3 en (cmos) 4 3835 2000 4260 v cc 3835 2000 4260 v cc 3835 2000 4260 v cc 3835 2000 4260 v cc mv v il input low voltage 1 d/d , en (pecl) 3 en (cmos) 4 3100 gnd 3525 800 3100 gnd 3525 800 3100 gnd 3525 800 3100 gnd 3525 800 mv v bb reference voltage 1 3610 3750 3610 3750 3610 3750 3610 3750 mv i ih input high current en 150 150 150 150 a i il input low current en (pecl) 3 en (cmos) 4 0.5 -150 0.5 -150 0.5 -150 0.5 -150 a i ee power supply current 2 34 34 34 37 ma 1. for supply voltages other that 5.0v, use the ec l table values and add supply voltage value. 2. specified with outputs terminated through 50 resistors to v cc - 2v. 3. en-sel connected to v ee through a 20k resistor 4. en-sel connected v ee or left open (nc) ac characteristics (v ee = -3.0v to -5.5v; v cc = gnd or v ee = gnd; v cc = +3.0v to +5.5v) -40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit t plh / t phl propagation delay d to q/q outputs 1 (se) en to q/q outputs 1,2 450 3000 450 3000 450 3000 450 3000 ps t skew duty cycle skew 3 (se) 5 20 5 20 5 20 5 20 ps v pp (ac) differential input swing 4 150 1000 150 1000 150 1000 150 1000 mv t r / t f output rise/fall 1 (20% - 80%) 100 240 100 240 100 240 100 240 ps 1. specified with outputs terminated through 50 resistors to v cc - 2v. 2. specified from 50% en input edge to v oh min or v ol max of the q/q outputs 3. duty cycle skew is the difference between a t plh and t phl propagation delay through a device. 4. the peak-to-peak differential input swing is the range for which ac parameters are guaranteed. th e device has a voltage gain of 100. ac pp input d d v pp (ac)
AZP94 april 2007 rev 1 www.azmicrotek.com 7 package diagram mlp 8 2x2mm bottom view side view mlp 8 (2x2mm) 2.0000.050 2.0000.050 pin 1 dot by marking 0.3500.050 pin 1 identification r0.100 typ 1.750 ref. 1.2000.050 exp. pad 1 2 3 4 5 6 7 8 0.2500.050 0.500 bsc 0.6000.050 exp. pad 123 4 0.7500.050 0.000-0.050 0.2030.025 top view note: all dimensions are in mm
AZP94 april 2007 rev 1 www.azmicrotek.com 8 arizona microtek, inc. reserves the right to change circuitry a nd specifications at any time without prior notice. arizona mic rotek, inc. makes no warranty, representation or guarant ee regarding the suitability of its products for any particular purpose, nor does a rizona microtek, inc. assume any liability arising out of the applica tion or use of any product or ci rcuit and specifically disclaims any and all liability, including without limitation special, consequential or inci dental damages. arizona microtek, inc. does not convey a ny license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as component s in systems intended to support or sustain life, or for any other application in which the fa ilure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should buye r purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall in demnify and hold arizona microtek, inc. and its officers, employees, subsidiaries, affiliates, and distributor s harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.
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